Team:Paris/Modeling/f4DC

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Strain Δ''flhDC'' and Δ''fliA''.

We assume that the logical gate is a ''SUM'' (see [[Team:Paris/Project|our project]]), so that 
<center> f4(FlhDC,FliA) = f4(FlhDC,0) + f4(0,FliA) </center>

[[Image:f4DCa.png]]

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